Design and Implementation of Low Leakage SRAM Acrhitectures using CMOS VLSI Circuits in Different Technology Environment

There is a demand for portable devices like mobiles and laptops etc. and their long battery life. For high integrity CMOS VLSI circuit design in deep submicron regime, feature size is reduced according to the improved technology. Reduced feature size devices need low power for their operation. Reduced power supply, reduces the threshold voltage of the device. Low threshold devices have improved performance but sub-threshold leakage current dominates in such a deep submicron regime.Reducing this leakage is a major challenge for CMOS VLSI circuit designers. Many leakage reduction techniques evolved to minimize this leakage. In this paper, we designed a basic one-bit SRAM cell usingsleepy-keeper combined leakage reduction technique in three different technology environments like 120nm, 90nm and 65 nm. Apart from one-bit SRAM cell, we also designed 64-bit SRAM architecture in above three technology environments. We are using Microwind software tool for simulation purpose. We are measuring and comparing the leakage power dissipationin different environments. We observed that improvement in the technology reduces the subthreshold leakage current and hence leakage power dissipation. Key-words: Sub-threshold leakage, Deep submicron regime, SRAM Architecture, 120nm, 90nm and 65nm technology environment.